[racket] Racket VM in FPGAs
No problem, glad to have referred you to the paper, I hope it'll be useful. Just for everybody else on the list, the paper URL is http://dspace.mit.edu/handle/1721.1/6334
> On Oct 19, 2013, at 4:08 PM, Petr Samarin <petrsamarin at gmail.com> wrote:
>
> To be more specific, initially I want to replace the Java VM in JOP with a Racket VM.
> JOP is great as a starting point because it has many useful things available from the start: support for USB and serial interfaces to load the bytecode from the PC, memory interfaces, floating point unit.
>
> I haven't looked into the Scheme-79 paper yet (thanks for the reference by the way!).
>
>> On Oct 19, 2013, at 1:35 PM, Alexander McLin wrote:
>> I'd be interested in hearing how it's going!
>>
>> Just curious, are you reusing ideas from Scheme-79, or starting off in an entirely different direction? From your original email, I assume you're using JOP as a springing board?
>>
>> Alex
>>
>>> On Oct 19, 2013, at 4:32 AM, Petr Samarin <petrsamarin at gmail.com> wrote:
>>>
>>> First I want to develop a small core (probably written in VHDL) that supports a subset of Racket's bytecode.
>>> I don't want to target any specific board/FPGA so that it can be used anywhere.
>>> But during development I will be testing the core on the board that I have at home (DE2-70 from Terrasic).
>>>
>>> When the basic version is done, I am also interested in how much parallelism can be achieved on the VM level (adding more stacks, executing several bytecodes at once, etc.).
>>>
>>> Petr
>>>
>>>> On Oct 19, 2013, at 12:26 AM, Neil Van Dyke wrote:
>>>> Petr, I will be very interested to hear how this project goes, including which FPGA you end up targeting, your application (large-scale parallel? low power?), and how speed compares to the JIT'd VM running on CPUs.
>>>>
>>>> If you can use an open source toolchain, all the better, although a free-as-in-beer toolchain would also be OK if the open source ones don't support your target. If it requires an expensive toolchain, it's still a good project, but much harder for other people to build on after you are done. (The beefier FPGAs I was looking at in the last year, for numeric computing, seemed to require expensive proprietary toolchains.)
>>>>
>>>> Neil V.
>>>
>>>
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