<html><head><meta http-equiv="content-type" content="text/html; charset=utf-8"></head><body dir="auto"><div>No problem, glad to have referred you to the paper, I hope it'll be useful. Just for everybody else on the list, the paper URL is <a href="http://dspace.mit.edu/handle/1721.1/6334">http://dspace.mit.edu/handle/1721.1/6334</a></div><div><br>On Oct 19, 2013, at 4:08 PM, Petr Samarin <<a href="mailto:petrsamarin@gmail.com">petrsamarin@gmail.com</a>> wrote:<br><br></div><blockquote type="cite"><div><span>To be more specific, initially I want to replace the Java VM in JOP with a Racket VM.</span><br><span>JOP is great as a starting point because it has many useful things available from the start: support for USB and serial interfaces to load the bytecode from the PC, memory interfaces, floating point unit.</span><br><span></span><br><span>I haven't looked into the Scheme-79 paper yet (thanks for the reference by the way!).</span><br><span></span><br><span>On Oct 19, 2013, at 1:35 PM, Alexander McLin wrote:</span><br><blockquote type="cite"><span>I'd be interested in hearing how it's going!</span><br></blockquote><blockquote type="cite"><span></span><br></blockquote><blockquote type="cite"><span>Just curious, are you reusing ideas from Scheme-79, or starting off in an entirely different direction? From your original email, I assume you're using JOP as a springing board?</span><br></blockquote><blockquote type="cite"><span></span><br></blockquote><blockquote type="cite"><span>Alex</span><br></blockquote><blockquote type="cite"><span></span><br></blockquote><blockquote type="cite"><blockquote type="cite"><span>On Oct 19, 2013, at 4:32 AM, Petr Samarin <<a href="mailto:petrsamarin@gmail.com">petrsamarin@gmail.com</a>> wrote:</span><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span></span><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span>First I want to develop a small core (probably written in VHDL) that supports a subset of Racket's bytecode.</span><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span>I don't want to target any specific board/FPGA so that it can be used anywhere.</span><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span>But during development I will be testing the core on the board that I have at home (DE2-70 from Terrasic).</span><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span></span><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span>When the basic version is done, I am also interested in how much parallelism can be achieved on the VM level (adding more stacks, executing several bytecodes at once, etc.).</span><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span></span><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span>Petr</span><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span></span><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span>On Oct 19, 2013, at 12:26 AM, Neil Van Dyke wrote:</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span>Petr, I will be very interested to hear how this project goes, including which FPGA you end up targeting, your application (large-scale parallel? low power?), and how speed compares to the JIT'd VM running on CPUs.</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span></span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span>If you can use an open source toolchain, all the better, although a free-as-in-beer toolchain would also be OK if the open source ones don't support your target. If it requires an expensive toolchain, it's still a good project, but much harder for other people to build on after you are done. (The beefier FPGAs I was looking at in the last year, for numeric computing, seemed to require expensive proprietary toolchains.)</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span></span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><blockquote type="cite"><span>Neil V.</span><br></blockquote></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span></span><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span></span><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span>____________________</span><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span>Racket Users list:</span><br></blockquote></blockquote><blockquote type="cite"><blockquote type="cite"><span><a href="http://lists.racket-lang.org/users">http://lists.racket-lang.org/users</a></span><br></blockquote></blockquote><span></span><br></div></blockquote></body></html>