[racket] Racket VM in FPGAs

From: Petr Samarin (petrsamarin at gmail.com)
Date: Sat Oct 19 04:32:03 EDT 2013

First I want to develop a small core (probably written in VHDL) that supports a subset of Racket's bytecode.
I don't want to target any specific board/FPGA so that it can be used anywhere.
But during development I will be testing the core on the board that I have at home (DE2-70 from Terrasic).

When the basic version is done, I am also interested in how much parallelism can be achieved on the VM level (adding more stacks, executing several bytecodes at once, etc.).


On Oct 19, 2013, at 12:26 AM, Neil Van Dyke wrote:
> Petr, I will be very interested to hear how this project goes, including which FPGA you end up targeting, your application (large-scale parallel?  low power?), and how speed compares to the JIT'd VM running on CPUs.
> If you can use an open source toolchain, all the better, although a free-as-in-beer toolchain would also be OK if the open source ones don't support your target.  If it requires an expensive toolchain, it's still a good project, but much harder for other people to build on after you are done.  (The beefier FPGAs I was looking at in the last year, for numeric computing, seemed to require expensive proprietary toolchains.)
> Neil V.

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