[plt-scheme] 3rd-8th Grade

From: Bill Wood (william.wood3 at comcast.net)
Date: Mon Mar 20 09:07:48 EST 2006

On Mon, 2006-03-20 at 05:18 -0800, Gregory Woodhouse wrote:
   . . .
> > One of the
> > EE's helped me discover that I could even design for performance!  It
> > turned out, for example, that short fat networks tended to have high
> > parallelism and short latency while long skinny networks tended to  
> > have
> > low parallelism and high latency.  Also, the "area" of a network
> > corresponded to the number of CPU's required.
> And isn't it interesting that this is a visual metaphor? Or is it?

Exactly.  The model of computation as flow of data through a circuit
fell right in line with their mental habit of thinking of digital
computation as flow of bits/bit-strings through a logic circuit.

 -- Bill Wood

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